Design and analysis of scan power reduction based on linear feedback shift register reseeding

Low power testing in VLSI has emerged as a standard idea in today´s electronics industry. The need for low power is root for a major pattern shift where power consumption has become a significant concern while comparing with performance and area. This work explores XOR network with Linear Feedback Shift Register (LFSR), which is having different tap connection. The proposed work is associated with general LFSR and modified LFSR with proper seed selection. This technique produces different input patterns and targeted to reduce transition switching of the bits. Experimental result is verified by XILINX Vertex 6 low power FPGA.