Novel binary divider architecture for high speed VLSI applications

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel Binary divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary recursion through Vedic division methodology. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx ISE using 9Onm CMOS technology. The propagation delay of the resulting 8-bit binary dividend by an 4-bit divisor circuitry was only ~19.9ns and consumed ~34mW power for a LUT Utilization of 23/1536. By combining Boolean logic with ancient Vedic mathematics, substantial amount of iteration were eliminated that resulted in ~46% reduction in delay and ~27% reduction in power compared with the mostly used (Repetitive subtraction method) architecture.