Intrinsic admittance parameter for separate gate InA1As/InGaAs DG-HEMT for 100 nm gate length

Author

Parveen ; Jogi, Jyotika ; Gupta, Madhu ; Gupta, R.S.

Author_Institution

Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India

fYear

2013

fDate

11-12 April 2013

Firstpage

750

Lastpage

754

Abstract

An analytical model for 3-port short circuit admittance parameter (V-parameter) for separate gate InAlAs/InGaAs/InP Double Gate High Electron Mobility Transistor (DG-HEMT) is presented in this paper. These admittance parameters are obtained in term of real and imaginary part from the 3-port equivalent circuit of the DG-HEMT and the effect of two gate voltage on the cut-off frequency of the DG-HEMT is studied. The analytical result obtained are compared with Atlas Silvaco Device simulator and found in a good agreement, thus validating the model.

Keywords

high electron mobility transistors; 3 port equivalent circuit; 3 port short circuit admittance parameter; Atlas Silvaco device simulator; DG HEMT; InAlAs-InGaAs; V parameter; cut off frequency; double gate high electron mobility transistor; intrinsic admittance parameter; separate gate; size 100 nm; Admittance; Cutoff frequency; Equivalent circuits; HEMTs; Indium gallium arsenide; Logic gates; 3-Port Equivlent Circuit; Separate Gate DG-HEMT; Silvaco Atlas 2D Device Simulator; Y-Parameter;

fLanguage

English

Publisher

ieee

Conference_Titel

Information & Communication Technologies (ICT), 2013 IEEE Conference on

Conference_Location

JeJu Island

Print_ISBN

978-1-4673-5759-3

Type

conf

DOI

10.1109/CICT.2013.6558194

Filename

6558194