A low offset fast settling rail-to-rail stable operational amplifier in 180 nm technology

Author

Dash, Aiswarya ; Mandal, Sajal Kumar ; Patro, B. Shivalal ; Anand, A.

Author_Institution

Sch. of Electron. Eng., KIIT Univ., Bhubaneswar, India

fYear

2013

fDate

11-12 April 2013

Firstpage

793

Lastpage

797

Abstract

This work presents the design of a modified two stage operational amplifier in 0.18 μm CMOS technology. The main objective of the design is to make a trade-off between offset voltage and power consumption while maintaining rail-to-rail output swing and high phase margin. For this purpose, transistors with controlled region of operation are included to the output stage. Simulation is done in Cadence Spectre with 1.8V power supply. Simulation results show that the designed OPAMP consumes 616.31 μW power with high phase margin of 70.6° and very low offset voltage of 16.91 μV, maintaining rail-to-rail output swing.

Keywords

CMOS analogue integrated circuits; operational amplifiers; power consumption; CMOS technology; OPAMP; cadence spectre; high phase margin; low offset fast settling rail-to-rail stable operational amplifier; offset voltage consumption; power 616.31 muW; power consumption; power supply; rail-to-rail output swing; size 180 nm; voltage 1.8 V; voltage 16.91 muV; CMOS integrated circuits; Conferences; Gain; Operational amplifiers; Rails; Simulation; Transistors; CMOS; OPAMP; Offset voltage; phase margin;

fLanguage

English

Publisher

ieee

Conference_Titel

Information & Communication Technologies (ICT), 2013 IEEE Conference on

Conference_Location

JeJu Island

Print_ISBN

978-1-4673-5759-3

Type

conf

DOI

10.1109/CICT.2013.6558202

Filename

6558202