Parallel processing architecture for micro-polygon rasterization

The shape of an object displayed on-screen is specified by a collection of triangles, or micro-polygons. Micro-polygons are defined by the (x,y,z) co-ordinates of the three vertices. Rasterization uses the vertex locations of the micropolygon to determine the co-ordinates of all the pixels covered by the micro-polygon on the display screen. A pixel is determined to be inside the micro-polygon by performing cross-product operations using the micro-polygon´s three vertices. This paper uses parallel processing architecture to reduce the total time required for rasterization operation. The micro-polygon is broken down into four quadrants and each quadrant is processed in parallel. The rasterization algorithm is modified so that the cross-product multiplication operations are needed only at the start of micro-polygon with subsequent pixels in micro-polygon handled using addition operations instead. Further, the cross-product multipliers are shared among the parallel processors. These optimizations allow significant improvement in processing power.