A high-speed circuit design for power reduction & evaluation contention minimization in wide fan-in OR gates

Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. As power consumption is directly proportional to the dynamic node capacitance, a new circuit technique is presented in this paper which employs the partitioning of dynamic node capacitance with the help of a splitter transistor to reduce the power consumption. With the help of a modified keeper circuitry, the contention between keeper and the pull down evaluation network is reduced drastically. Simulation results show a reduction of 78.91 % when compared to the Conditional Keeper (CKP) technique and reduction by 65.51 % when compared with the Adaptive Pseudo Dual Keeper (APDK) scheme. The reduction is about 83.56 % when compared to CKP and 70.27 % when pitted against the APDK when the issue of contention current is taken up. The reduction in power and contention current is found to be true when the design concept was tested for a 32 bit comparator circuitry. Simulations have been performed using the SILVACO EDA tool on a 32-bit wide fan-in OR gate in 32nm process technology at a frequency of 1.5 GHz and supply voltage of 0.9V. Monte Carlo simulations have also been performed to test an idea which makes the circuit tolerant to process variations.