Through silicon via admittance field solver of system level capacity: Theory

A novel methodology, relying on the often used method of moments (MoM), is developed for the admittance extraction (capacitance/conductance), of the emerging technology of three dimensional integrated circuits (3D-ICs). Our formulation has as unknown quantities the potential and the electric displacement field inside the dielectrics (isolation, depletion region) surrounding the through silicon vias (TSVs). The integral equations, which define the problem, are discretized according to the MoM framework. From the solution of the MoM linear system of equations it is straightforward to compute the desired capacitance(s). The discretization of the unknown quantities is performed so efficiently that, even for strict error criteria, the resulting linear system of equation is very compact. In addition, all the coefficients of the linear system are expressed in closed form. The two aforementioned properties are the key in delivering as a striking novelty a very fast and accurate solver for TSV admittance extraction. We present within this formalism, accurate accounting of substrate effects, frequency dependence of capacitance, depletion region effects, and capacitive coupling among TSVs and copper pillars. Whole families of emerging technologies can be analyzed within the proposed methodology and accompanying solver.