DocumentCode
618508
Title
An innovative simulation workflow for debugging high-speed digital designs using jitter separation
Author
Chastang, C. ; Amedeo, Alexandre ; Poisson, V. ; Grison, P. ; Demuynck, F. ; Gautier, Cyrille ; Costa, Francois
Author_Institution
Thales Commun. & Security, Gennevilliers, France
fYear
2013
fDate
12-15 May 2013
Firstpage
1
Lastpage
4
Abstract
This paper presents a new simulation workflow for jitter separation analysis. Jitter separation is a very promising tool that quickly identifies the sources of signal integrity degradation and thus enables easy optimization of a design to meet the low jitter requirements of multi-gigabit high speed digital SERDES devices.
Keywords
electronic engineering computing; high-speed integrated circuits; integrated circuit design; high-speed digital design debugging; innovative simulation workflow; jitter separation analysis; low-jitter requirements; multigigabit high-speed digital SERDES devices; signal integrity degradation; Analytical models; Computational modeling; Conductors; Crosstalk; Impedance; Jitter; Noise; IBIS AMI; crosstalk; high-speed; jitter; noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal and Power Integrity (SPI), 2013 17th IEEE Workshop on
Conference_Location
Paris
Print_ISBN
978-1-4673-5678-7
Type
conf
DOI
10.1109/SaPIW.2013.6558319
Filename
6558319
Link To Document