• DocumentCode
    618551
  • Title

    GCA: Global congestion awareness for load balance in Networks-on-Chip

  • Author

    Ramakrishna, M. ; Gratz, Paul V. ; Sprintson, Alex

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
  • fYear
    2013
  • fDate
    21-24 April 2013
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    As modern CMPs scale to ever increasing core counts, Networks-on-Chip (NoCs) are emerging as an interconnection fabric, enabling communication between components. While NoCs provide high and scalable bandwidth, current routing algorithms, such as dimension-ordered routing, suffer from poor load balance, leading to reduced throughput and high latencies. Improving load balance, hence, is critical in future CMP designs where increased latency leads to wasted power and energy waiting for outstanding requests to resolve. Adaptive routing is a known technique to improve load balance, however, prior adaptive routing techniques either use local or regionally aggregated information to form their routing decisions. This paper proposes a new, light-weight, adaptive routing algorithm for on-chip routers based on global link state and congestion information, Global Congestion Awareness (GCA). GCA uses a simple, low-complexity route calculation unit, to calculate paths to their destination without the myopia of local decisions, nor the aggregation of unrelated status information, found in prior designs. In particular GCA outperforms local adaptive routing by 26%, Regional Congestion Awareness (RCA) by 15%, and a recent competing adaptive routing algorithm, DAR, by 8% on average on realistic workloads.
  • Keywords
    network routing; network-on-chip; CMP design; GCA; NoC; RCA; adaptive routing; congestion information; dimension-ordered routing; global congestion awareness; global link state; light-weight algorithm; load balance; network-on-chip; on-chip router; regional congestion awareness; Algorithm design and analysis; Complexity theory; Computer architecture; Measurement; Ports (Computers); Routing; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networks on Chip (NoCS), 2013 Seventh IEEE/ACM International Symposium on
  • Conference_Location
    Tempe, AZ
  • Print_ISBN
    978-1-4673-6491-1
  • Electronic_ISBN
    978-1-4673-6492-8
  • Type

    conf

  • DOI
    10.1109/NoCS.2013.6558405
  • Filename
    6558405