Reliability of a typical TSV structure with thermal bias

TSV (Through Silicon Via) technology has been employed on packaging for CIS (CMOS Image Sensor) chips for many years. To assess the reliability behavior of a typical TSV design for CIS chips, the temperature humidity cycling tests (THCT) have been performed on self designed TSV samples but without current bias. Since the current bias lead electromigration effects which are not neglect-able in actual CIS packaging applications, this study performs the thermal bias reliability tests on the same TSV chips. To this end, thermal aging and thermal cycling experiments with current bias were first performed, and resistance of the TSV samples were recorded continuously to identify the failure time of each sample. We next use the Weibull model for reliability analyses and the Weibull parameters were then extracted from the experimental data to predict lifetime performance of the samples. This paper finally compares the thermal biasing results in this study with the previous non-bias data.