Title :
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Author :
Kuan-Hsien Ho ; Hung-Chih Ou ; Yao-Wen Chang ; Hui-Fang Tsao
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
May 29 2013-June 7 2013
Abstract :
Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs.
Keywords :
analogue integrated circuits; capacitance; capacitor switching; integrated circuit design; integrated circuit interconnections; minimisation; nanoelectronics; network routing; network topology; analog integrated circuit; capacitance ratio mismatch; capacitor array; circuit interconnection; classical wirelength minimization problem; coupling aware length ratio matching routing; nanometer era; parasitic effect; route unit capacitor; switched capacitor circuit; topology generation; Capacitance; Capacitors; Couplings; Routing; Steiner trees; Tiles; Topology; Analog ICs; Physical Design; Routing;
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location :
Austin, TX