DocumentCode
619461
Title
Memory partitioning for multidimensional arrays in high-level synthesis
Author
Yuxin Wang ; Peng Li ; Peng Zhang ; Chen Zhang ; Cong, J.
Author_Institution
Comput. Sci. Dept., Peking Univ., Beijing, China
fYear
2013
fDate
May 29 2013-June 7 2013
Firstpage
1
Lastpage
8
Abstract
Memory partitioning is widely adopted to efficiently increase the memory bandwidth by using multiple memory banks and reducing data access conflict. Previous methods for memory partitioning mainly focused on one-dimensional arrays. As a consequence, designers must flatten a multidimensional array to fit those methodologies. In this work we propose an automatic memory partitioning scheme for multidimensional arrays based on linear transformation to provide high data throughput of on-chip memories for the loop pipelining in high-level synthesis. An optimal solution based on Ehrhart points counting is presented, and a heuristic solution based on memory padding is proposed to achieve a near optimal solution with a small logic overhead. Compared to the previous one-dimensional partitioning work, the experimental results show that our approach saves up to 21% of block RAMs, 19% in slices, and 46% in DSPs.
Keywords
information retrieval; storage management; DSP; Ehrhart points; automatic memory partitioning scheme; block RAM; data access conflict reduction; data throughput; heuristic solution; high-level synthesis; linear transformation; logic overhead; loop pipelining; memory bandwidth increment; memory padding; multidimensional arrays; multiple memory banks; on-chip memories; one-dimensional arrays; optimal solution; slices; Algorithm design and analysis; Arrays; Benchmark testing; Memory management; Partitioning algorithms; Random access memory; Vectors; High-Level Synthesis; Memory Padding; Memory Partitioning;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location
Austin, TX
ISSN
0738-100X
Type
conf
Filename
6560605
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