Title :
Towards structured ASICs using polarity-tunable Si nanowire transistors
Author :
Gaillardon, Pierre-Emmanuel ; De Marchi, Michele ; Amaru, Luca ; Bobba, Shashikanth ; Sacchetto, Davide ; Leblebici, Yusuf ; De Micheli, G.
Author_Institution :
Integrated Syst. Lab. (LSI), EPFL, Lausanne, Switzerland
fDate :
May 29 2013-June 7 2013
Abstract :
In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type characteristics simultaneously. This phenomenon can be tamed using double-gate structures. In this paper, we present a complete framework relying on Double-Gate-all-around Vertically stacked NanoWire FETs (DG-NWFETs). Such device enables a compact realization of arithmetic logic functions and presents unprecedented interest for structured ASIC applications.
Keywords :
application specific integrated circuits; elemental semiconductors; field effect transistors; integrated circuit design; logic circuits; nanowires; silicon; CMOS technology; DG-NWFET; Si; ambipolar behavior; arithmetic logic function; double-gate-all-around vertically stacked nanowire FET; n-type characteristics; p-type characteristics; polarity-tunable nanowire transistor; semiconductor device; structured ASIC application; CMOS integrated circuits; Design automation; Field effect transistors; Logic functions; Logic gates; Silicon; Nanowire transistors; XOR logic synthesis; controllable polarity; regular fabrics;
Conference_Titel :
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE
Conference_Location :
Austin, TX
