Abstract :
IC performance, power dissipation, size, and signal integrity are now dominated by interconnects. However, with ever-shrinking standard cells, blind minimization of interconnect during placement causes routing failures. Hence, we develop Coordinated Placeand-Route (CoPR) with (i) a Lightweight Incremental Routing Estimation (LIRE) frequently invoked during placement, (ii) placement techniques that address three types of routing congestion, and (iii) an interface to congestion estimation that supports new types of incrementality. LIRE comprehends routing obstacles and nonuniform routing capacities, and relies on a cache-friendly, fully incremental routing algorithm. Our implementation extends and improves our winning entry at the ICCAD 2012 Contest.
Keywords :
failure analysis; integrated circuit interconnections; network routing; CoPR complexity; IC performance; LIRE; coordinated place-and-route complexity; ever-shrinking standard cells; fully incremental routing algorithm; interconnect blind minimization; lightweight incremental routing estimation; placement techniques; power dissipation; routing congestion; routing failures; Benchmark testing; Complexity theory; Estimation; Layout; Optimization; Routing; Runtime;
