An accurate semi-analytical framework for full-chip TSV-induced stress modeling

TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis for the stress of simple TSV placement, but is not scalable to larger designs due to its expensive memory consumption and high run time. On the contrary, linear superposition method is efficient to analyze stress in full-chip scale, but sometimes it fails to provide an accurate estimation since it neglects the stress induced by interactions between TSVs. In this paper we propose an accurate two-stage semi-analytical framework for fullchip TSV-induced stress modeling. In addition to the linear superposition, we characterize the stress induced by interactions between TSVs to provide more accurate full-chip modeling. Experimental results demonstrate that the proposed framework can significantly improve the accuracy of linear superposition method with reasonable overhead in run time.