Design of delay line of automatically controlling message cache time

According to the practical issue that the fixed time relationship between keying signal and message signal of the transmitting terminal is failed to adapt to the every signal channel some transmitters get through, this thesis designs a type of delay line which can automatically control the message cache time. Also, this paper conducts several analyses in numerous aspects, such as design philosophy, hardware frame, logic control, time sequence list, etc. Meanwhile, this kind of delay line is characterized by long time delay, automatic control of delay time and so forth.