Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module

Author

Warnock, J. ; Yuen Chan ; Harrer, Hubert ; Carey, Sean ; Salem, Gerard ; Malone, David ; Puri, R. ; Zitz, Jeffrey A. ; Jatkowski, A. ; Strevig, G. ; Datta, Amitava ; Gattiker, Anne ; Bansal, Ankur ; Mayer, G. ; Yiu-Hing Chan ; Mayo, M. ; Rude, David L. ;

Author_Institution

IBM Syst. & Technol. Group, Yorktown Heights, NY, USA

Volume

49

Issue

1

fYear

2014

fDate

Jan. 2014

Firstpage

9

Lastpage

18

Abstract

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM´s high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

Keywords

DRAM chips; circuit tuning; elemental semiconductors; glass ceramics; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; microprocessor chips; microwave integrated circuits; multichip modules; silicon; silicon-on-insulator; CP; IBM high-performance high-k-metal-gate SOI technology; SC; Si; circuit design; clocking; eDRAM cache; frequency 5.5 GHz; frequency tuning; high-bandwidth low-latency interconnection; high-performance glass-ceramic substrate; level-4 cache chip; memory size 192 MByte; multichip module; reliability; size 32 nm; size 45 nm; super-scalar out-of-order processor core; thermal modeling; zEnterprise EC12 microprocessor chip; Arrays; Clocks; Delays; Hardware; Integrated circuit modeling; Reliability engineering; 32 nm SOI; CMOS digital integrated circuits; Chip integration; EC12; NBTI; PBTI; SRAM; VLSI design; ZEC12; chip thermal modeling; circuit design methodology; clock distribution; clock grid; design for reliability; design for test; digital circuits; high-frequency CMOS design; high-k/metal-gate; microprocessor test; microprocessors; multi-chip module; power efficiency; reliability; structured synthesis; system z; zEnterprise;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2284647

Filename

6644318