Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs

This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.