DocumentCode
621094
Title
Low-cost DC BIST for analog circuits: A case study
Author
Petrashin, Pablo ; Dualibe, Carlos ; Lancioni, Walter ; Toledo, Luis
Author_Institution
Microelectron. Lab., Catholic Univ. of Cordoba, Cordoba, Argentina
fYear
2013
fDate
3-5 April 2013
Firstpage
1
Lastpage
4
Abstract
This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.
Keywords
analogue integrated circuits; built-in self test; integrated circuit testing; low-power electronics; DC analog testing; analog circuits; catastrophic fault; fault coverage; fault driven testing; low-cost DC BIST; low-voltage transconductor; parametric fault; sensitivity-to-faults node; size 65 nm; structural testing; Correlation; Logic gates; MATLAB; Reliability; Testing; BIST; DFT; analog testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop (LATW), 2013 14th Latin American
Conference_Location
Cordoba
Print_ISBN
978-1-4799-0595-9
Type
conf
DOI
10.1109/LATW.2013.6562668
Filename
6562668
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