Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs

Technology scaling has made possible the integration of millions of transistors into a small area. The consequent increase of memory´s density generated new types of defects during the manufacturing process that have become important concerns for the testing of Nano-Scale Static Random Access Memories (SRAMs). The rapidly increasing need to store more information results in the fact that the memory elements occupy great part of the Systemon-Chip´s (SoC) silicon area. In this context, a technique based on On-Chip Current Sensors (OCCS) and Neighbourhood Comparison Logic (NCL) to detect resistive-open defects in SRAMs is proposed. The main idea behind the hardware-based technique is to explore the evaluation throughout an analysis of the current of neighbouring SRAM cells in order to identify the presence of manufacturing defects. Experimental results obtained throughout simulations demonstrate the technique´s efficiency. Finally, an analysis of the overheads makes possible the comparison with today´s standard techniques.