Evaluating analog circuit performance in light of MOSFET aging at different time scales

A flow is presented to evaluate analog CMOS circuit performance pending temporal MOSFET degradation. The change in threshold voltage due to the bias temperature instability (BTI) mechanism is used as a paradigm. The tasks of performance evaluation and MOSFET degradation are decoupled in the flow. This is extended to severalize the model of degradation at three time scales: that of signal processing, electrical stress and recovery cycles, and circuit lifetime. The aim is to allow the use of diverse models in each time scale, and to simulate circuit performance with less computational cost.