DocumentCode :
621260
Title :
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits
Author :
Shao-Yu Yang ; Yin-Nien Chen ; Ming-Long Fan ; Hu, Vita Pi-Ho ; Pin Su ; Ching-Te Chuang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2013
fDate :
29-31 May 2013
Firstpage :
61
Lastpage :
64
Abstract :
In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on the drain current, stability of 6T SRAM cells and logic circuits of Si and Ge NanoWire (NW) FETs. The trap position dependence of the RTN amplitude (ΔIds/Ids) along the channel length direction is examined. For Si-NW FET, significant RTN impact is observed for trap located near the middle region of channel between the source/drain (worst position), while for Ge-NW FET, the worst position depends on the drain bias (Vds) and gate bias (Vgs). The RTN amplitude of Ge-NW FET exhibits distinctly different Vgs and Vds dependence compared with the Si-NW FET due to lower bandgap, higher permittivity, and band-to-band tunneling at the drain in Ge-NW FET. In particular, it is found that Ge-NW FET may exhibit negative RTN amplitude (Ids increases) with acceptor type trap due to the reduction of band-to-band tunneling length when the trap is located near the drain. Ge-NW FET shows larger Vdd dependence of the RTN amplitude variation. For 6T NW SRAM cell, the READ Static Noise Noise Margin (RSNM) of 64 combinations from trapping/de-trapping state in each cell transistor is examined. The impact of RTN on the leakage of NW inverter is investigated using 3D atomistic TCAD mixed-mode simulations.
Keywords :
SRAM chips; elemental semiconductors; field effect transistors; germanium; integrated circuit noise; logic circuits; nanowires; random noise; semiconductor device noise; silicon; 3D atomistic TCAD mixed-mode simulations; 6T NW SRAM cell; 6T SRAM cell stability; Ge; NW inverter; RTN amplitude variation; Si; acceptor-type trap; band-to-band tunneling length reduction; channel length direction; drain bias; drain current; gate bias; germanium NW FET; germanium nanowire FET; logic circuits; read static noise noise margin; silicon NW FET; silicon nanowire FET; single-trap induced RTN; single-trap induced random telegraph noise; trap position dependence; trapping-de-trapping state; Electron traps; Field effect transistors; Inverters; SRAM cells; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location :
Pavia
Print_ISBN :
978-1-4673-4740-2
Electronic_ISBN :
978-1-4673-4741-9
Type :
conf
DOI :
10.1109/ICICDT.2013.6563303
Filename :
6563303
Link To Document :
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