Title :
Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration
Author :
Sadaka, Mariam ; Radu, Iuliana ; Lagahe-Blanchard, Chrystelle ; Di Cioccio, L.
Author_Institution :
Soitec USA Inc., Austin, TX, USA
Abstract :
The wafer stacking technology for 3D integration requires high quality bonding interfaces with uniform bonding films. Two wafer level stacking technologies - Smart Stacking™ and Smart Cut™ - are developed to address the manufacturing challenges for improved process cost efficiency.
Keywords :
integrated circuit manufacture; three-dimensional integrated circuits; wafer bonding; wafer-scale integration; 3D integration; Smart Cut; Smart Stacking; high quality bonding interfaces; process cost efficiency; uniform bonding films; wafer stacking technology; Bonding; Dielectrics; Metals; Silicon; Stacking; Surface treatment; Throughput; 3D wafer stacking; high density integration; low temperature bonding; non-thermo-compression metal bonding; sub-micron alignment;
Conference_Titel :
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location :
Pavia
Print_ISBN :
978-1-4673-4740-2
Electronic_ISBN :
978-1-4673-4741-9
DOI :
10.1109/ICICDT.2013.6563343
