A 14-bit and 70-dB dynamic range, continuous time, sigma delta modulator

This paper presents a new circuit realization for multi bit continuous time sigma delta modulator. The converter has been designed in a 0.18 um TSMC technology and achieves a maximum signal-to-noise ratio (SNR) of 70 dB in a 1 MHz bandwidth and dissipates 5mW from a 1.8 V supply when clocked at 100MHz. The convertor has a third-order active-RC loop filter, a 4-bit flash quantizer and errors are corrected by Data Weighted Averaging (DWA). The DWA technique is used for reducing DAC noise due to component mismatches. A multi-bit non-return-to-zero (NRZ) DACs is adopted to reduce clock jitter sensitivity. The performance of the circuits was demonstrated using HSPICE at low voltage operation of 1.8V.