An FPGA implementation of the SHA-3: The BLAKE hash function

Following the attacks considerable standard SHA-2, In this paper, a new version of hash was developed known as SHA-3. We discussed the study of the SHA-3 hash exposing the protocol chosen for our is BLAKE-256 application. The optimization of this function and all steps taken to achieve this implementation was done are performed the synthesis of IP hash and optimization. The resulting hardware requirements as well the computation time are presented and compared with previous work. A comparison between our implementation SHA3 and the Blake 256; the proposed design is implemented on the most recent Xilinx Virtex FPGAs. The number of occupied slices, the maximum working frequency (in megahertz), the throughput (in gigabits per second), and the efficiency (in gigabits per second/slice) have been compared. An FPGA architectural for BLAKE-256 was developed using VHDL, and synthesized using Virtex-5, Virtex-6 and Virtex-7 chips. Blake-256 show tremendous throughput increase of 179% when compared with the implementation of the original Blake -256.