Title :
An effective CMOS Charge Pump-Phase Frequency Detector Circuit for PLLs applications
Author :
Toihria, Intissar ; Ayadi, Rajaa ; Masmoudi, Malek
Author_Institution :
Lab. of El ectronic & Micro-Technol. Commun. (EMC), Univ. of Sfax, Sfax, Tunisia
Abstract :
Charge Pump controlled with three states of a Phase Frequency Detector is an essential building block of Phase Locked Loops (PLLs). Charge Pump-Phase Locked Loops are usually used in diverse applications, such as on chip clock synthesis, symbol timing recovery for serial data streams and generation of frequency agile high frequency carrier signals. This paper describes an effective structure of a Charge Pump (CP) and a Phase Frequency Detector (PFD) circuits which are the key blocks for the design of PLLs. The behavioral modeling has been synthesized from a hardware description language (VHDL-AMS). This CP-PFD circuit was designed with 0.35μm AMS CMOS technology. Electrical simulation results are shown using ADS platform.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; charge pump circuits; phase locked loops; AMS CMOS technology; CMOS charge pump-phase frequency detector circuit; CP-PFD circuit; PLL application; VHDL-AMS; behavioral modeling; charge pump-phase locked loops; chip clock synthesis; electrical simulation; frequency-agile high-frequency carrier signals; hardware description language; serial data streams; size 0.35 mum; symbol timing recovery; CMOS integrated circuits; Charge pumps; Integrated circuit modeling; Phase frequency detector; Phase locked loops; Transistors; Voltage-controlled oscillators; Behaviors Modeling; CMOS 0.35µm AMS technology; Charge Pump; Mixed Analog Design; Phase Frequency Detector; VHDLAMS;
Conference_Titel :
Systems, Signals & Devices (SSD), 2013 10th International Multi-Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4673-6459-1
Electronic_ISBN :
978-1-4673-6458-4
DOI :
10.1109/SSD.2013.6564155
