DocumentCode :
623770
Title :
An optimized design of reconfigurable PSD accelerator for online shrew DDoS attacks detection
Author :
Hao Chen ; Yu Chen ; Summerville, Douglas H. ; Zhou Su
Author_Institution :
Dept. of Electr. & Comput. Eng., SUNY - Binghamton, Binghamton, NY, USA
fYear :
2013
fDate :
14-19 April 2013
Firstpage :
1780
Lastpage :
1787
Abstract :
Shrew Distributed Denial-of-Service (DDoS) attacks are stealthy, concealing their malicious activities in normal traffic. Although it is difficult to detect shrew DDoS attacks in the time domain, the existent energy exposes them in frequency domain. For this purpose, online Power Spectral Density (PSD) analysis necessitates real-time PSD data conversion. In this paper, an optimized FPGA based accelerator for real-time PSD conversion is proposed, which is based on our innovative component-reusable Auto-Correlation (AC) algorithm and the adapted 2N-point real-valued Discrete Fourier Transform (DFT) algorithm. Further optimization is achieved through the exploration of algorithm characteristics and hardware parallelism for this case. Evaluation results from both simulation and synthesis are provided. The overall design can be easily placed in a Xilinx Virtex2 Pro FGPA.
Keywords :
computer network security; discrete Fourier transforms; electronic data interchange; field programmable gate arrays; frequency-domain analysis; parallel processing; reconfigurable architectures; telecommunication traffic; 2N-point real-valued discrete Fourier transform algorithm; AC algorithm; DFT algorithm; Xilinx Virtex2 Pro FGPA; component-reusable auto-correlation algorithm; frequency domain; hardware parallelism; malicious activities; normal traffic; online power spectral density analysis; online shrew DDoS attack detection; optimized FPGA based accelerator; real-time PSD data conversion; reconfigurable PSD accelerator optimized design; shrew distributed denial-of-service attacks; Algorithm design and analysis; Computer crime; Convolution; Discrete Fourier transforms; Field programmable gate arrays; Frequency-domain analysis; Real-time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
INFOCOM, 2013 Proceedings IEEE
Conference_Location :
Turin
ISSN :
0743-166X
Print_ISBN :
978-1-4673-5944-3
Type :
conf
DOI :
10.1109/INFCOM.2013.6566976
Filename :
6566976
Link To Document :
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