Time-predictable DRAM access scheduling algorithms for real-time multicore processors

In this paper, we propose a time-predictable memory scheduling algorithm called the RT-balance policy for DRAM memory accesses. It can estimate the WCET of DRAM accesses from a real-time task more tightly than using the longest delay in pessimistic WCET analysis. Furthermore, to get more precise bound for memory accesses of a real-time thread, the RT-bypass policy is proposed. Our experiments indicate that compared to the FR-FCFS memory scheduling algorithm, the RT-balance and the RT bypass memory scheduling algorithms lead to much simpler and more accurate WCET analysis, but may decrease the DRAM performance by 28.6% and 36.7% respectively.