Title :
Synthesizing and integrating TSE with hard core TCP/IP for smart grid
Author :
Amiri, Rami ; Elkeelany, Omar
Abstract :
In this research, we develop a high-performance reliable communication platform. The platform consists of two parts, TCP/IP protocol stack that is implemented as hardware on an FPGA. And the second part is an integrated Triple-speed Ethernet (TSE). We designed a state machine that configures TSE and an Ethernet frame generator to send TCP/IP packets at 1 Gbps, which are then driven into Logic Analyzer for a design synthesis and verification process.
Keywords :
computer network performance evaluation; field programmable gate arrays; finite state machines; local area networks; logic analysers; smart power grids; transport protocols; Ethernet frame generator; FPGA; TCP/IP packets; TSE synthesis; design synthesis; hard core TCP/IP protocol stack; high-performance reliable communication platform; integrated triple-speed Ethernet; logic analyzer; smart grid; state machine; verification process; Field programmable gate arrays; Generators; Hardware; IP networks; Internet; Protocols; Smart grids; Altera Triple-speed Ethernet; Ethernet Generator; Gigabit;
Conference_Titel :
Southeastcon, 2013 Proceedings of IEEE
Conference_Location :
Jacksonville, FL
Print_ISBN :
978-1-4799-0052-7
DOI :
10.1109/SECON.2013.6567389
