Architecture exploration of a heterogeneous embedded processor for the smart grid

Implementing the smart grid will require intelligent interaction between the power generating and consuming devices, which is achieved by installing devices capable of processing data and communicating it to various parts in the grid. The role of embedded processors will be to achieve high performance in the given real time situations. The embedded processors carry out tasks similar to security encryption, signal processing, power flow calculation etc. which are essential for data analysis and proper data transmission. Depending on where the embedded processor is in the smart grid hierarchy, the application running on the processor will be different. We show by qualitative analysis that there is a need for a new design in the micro-architecture of the processors. The method to develop this processor for the smart grid applications is discussed, this includes identifying the benchmarks, customizing the architecture for them and then finding the optimized configuration for the processor. We come up with a possible design for the embedded processor, for which performance is measured and optimized using a cycle accurate processor architecture simulator.