DocumentCode :
624333
Title :
iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration
Author :
Geng Zheng ; Mohanty, S.P. ; Kougianos, E. ; Okobiah, O.
Author_Institution :
NanoSystem Design Lab., Univ. of North Texas, Denton, TX, USA
fYear :
2013
fDate :
5-7 June 2013
Firstpage :
75
Lastpage :
78
Abstract :
The gap between abstraction levels in analog design is a major obstacle for advancing analog and mixed-signal design automation. Intelligent surrogate models for low-level analog building blocks are needed to bridge behavioral and transistor-level simulations. With this objective, artificial neural network (ANN) metamodels are incorporated in Verilog-AMS to capture the highly nonlinear response of the analog block. Parameterized ANN Verilog-AMS behavioral metamodels are constructed for efficient system-level design exploration. The application of these intelligent metamodels to multi-objective analog block optimization is demonstrated. To the best of the authors´ knowledge this is the first paper to integrate artificial neural network models in Verilog-AMS. To demonstrate the application of iVAMS, a biologically-inspired “firefly optimization algorithm” is applied to an OP-AMP design. The optimization process is sped up by 5580× due to the use of iVAMS with negligible loss in accuracy.
Keywords :
electronic engineering computing; hardware description languages; neural nets; operational amplifiers; optimisation; signal processing; ANN metamodels; OP-AMP design; Verilog-AMS; advancing analog; analog block; analog design; artificial neural network; biologically inspired firefly optimization algorithm; bridge behavioral simulations; circuit accurate system level mixed signal design exploration; iVAMS; intelligent metamodel integrated verilog AMS; intelligent surrogate models; mixed signal design automation; multiobjective analog block optimization; optimization process; transistor level simulations; Accuracy; Algorithm design and analysis; Artificial neural networks; Design automation; Hardware design languages; Integrated circuit modeling; Optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on
Conference_Location :
Washington, DC
ISSN :
2160-0511
Print_ISBN :
978-1-4799-0494-5
Type :
conf
DOI :
10.1109/ASAP.2013.6567553
Filename :
6567553
Link To Document :
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