Title :
Fused floating-point two-term sum-of-squares unit
Author :
Jae Hong Min ; Swartzlander, Earl E.
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Texas at Austin, Austin, TX, USA
Abstract :
This paper proposes a low-power and high-performance fused floating-point two-term sum-of-squares (fused SoSQ) unit and compares it with discrete and fused dot-product units containing normal significand multipliers and discrete sum-of-squares units containing significand squarers; with these units, sum-of-squares is computed. The fused sum-of-squares unit has less latency, area, and power consumption than the floating-point dot-product units and the discrete parallel sum-of-squares unit. The main reason is that a fused floating-point architecture is used, its significand squarer is faster and smaller than normal significand multipliers, and the sub-modules related to subtraction can be removed. Furthermore, compound addition can be applied to the fused sum-of-squares unit to enhance the performance in the single-path addition. Compared with the fused floating-point dot-product, the fused floating-point sum-of-squares unit with the compound addition has 54% less power consumption, 48% less area, and 44% less latency.
Keywords :
floating point arithmetic; low-power electronics; multiplying circuits; power consumption; summing circuits; compound addition; discrete dot-product unit; discrete parallel sum-of-squares unit; discrete sum-of-squares unit; fused SoSQ unit; fused dot-product unit; fused floating-point architecture; fused floating-point dot-product unit; high-performance fused floating-point two-term sum-of-squares unit; low-power fused floating-point two-term sum-of-squares unit; normal significand multiplier; power consumption; significand squarers; single-path addition performance; Adders; Arrays; Compounds; Delays; Floating-point arithmetic; Power demand; fused floating-point arithmetic unit; low-power floating-point arithmetic unit; two-term sum-of-squares unit;
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4799-0494-5
DOI :
10.1109/ASAP.2013.6567568