Implementing high-performance, low-power FPGA-based optical flow accelerators in C

Author

Monson, Josh ; Wirthlin, Michael ; Hutchings, Brad L.

Author_Institution

Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA

fYear

2013

fDate

5-7 June 2013

Firstpage

363

Lastpage

369

Abstract

Recent developments in High-Level Synthesis (HLS) for FPGAs are making it possible to “run” C code on FPGAs thereby making modern programming environments available to FPGA developers. In this paper, C code for a complex optical-flow algorithm is optimized for both a desktop PC and for an FPGA-based system, the Xilinx Zynq-7000, a device containing both a programmable fabric and two ARM cores. The paper discusses how the code is optimized and restructured to execute effectively on the programmable fabric and the ARM cores. The resulting Zynq version of the C code is competitive with the desktop PC but only consumes 1/7th as much energy.

Keywords

C language; circuit optimisation; electronic engineering computing; field programmable gate arrays; high level synthesis; logic design; low-power electronics; microprocessor chips; programming environments; ARM core; C code; FPGA-based system; HLS; Xilinx Zynq-7000; complex optical-flow algorithm; desktop PC; high-level synthesis; low-power FPGA; optical flow accelerator; optimization; programmable fabric; programming environment; Acceleration; Biomedical optical imaging; Fabrics; Field programmable gate arrays; Hardware; Optical imaging; Real-time systems; ARM; FPGA; configurable computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on

Conference_Location

Washington, DC

ISSN

2160-0511

Print_ISBN

978-1-4799-0494-5

Type

conf

DOI

10.1109/ASAP.2013.6567602

Filename

6567602