Spur analysis and reduction of edge combining DLL-based frequency multiplier

A detailed study of reference frequency spurious spectrum components in edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this paper. The reference spur components caused by the delay mismatch between delay cells in the voltage controlled delay line (VCDL), as well as the spur components due to phase detector locking error are analyzed and unified. A digital calibration method is proposed to lower the spurious tone for the DLL based frequency multiplier output. An error detector compares the timing difference of each sub-period and compensates for the error by adjusting the delay time of each delay cell. The simulation results show a reduction of reference spur.