Author_Institution :
Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697-3435, USA
Abstract :
The emergence of many-core platforms increases the need for high memory bandwidth, which in turn creates the need for vast amounts of on-chip memory space. Designers must carefully provision the on-chip memory resources to meet application needs. Efficient memory management is extremely critical since it has a great impact on the system´s power consumption and throughput. While memory hierarchies have traditionally been based on SRAM-based on-chip caches, the demands of predictability, low power/energy, as well as the emergence of non-volatile memories (NVMs) and mixed-criticality systems, have led to increasing use of software-controlled on-chip memories. The talk presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the disparate challenges faced by designers in deploying such memory subsystems (e.g., sharing memory resources, handling variability, and deploying heterogeneous memory families). The overall approach revisits and extends the classical notion of clouds and memory virtualization to handle scalable on-chip memory organizations for reduced power consumption, security, reliability and yield management.