DocumentCode :
625251
Title :
Utilizing circuit structure for scan chain diagnosis
Author :
Wei-Hen Lo ; Ang-Chih Hsieh ; Chien-Ming Lan ; Min-Hsien Lin ; TingTing Hwang
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2013
fDate :
27-30 May 2013
Firstpage :
1
Lastpage :
6
Abstract :
Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip flops. After partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC´99 benchmarks.
Keywords :
controllability; fault diagnosis; flip-flops; logic circuits; ITC´99 benchmark; bipartite matching reordering algorithm; circuit structure; flip flop; scan cell; scan chain fault diagnosis resolution; scan chain partitioning algorithm; scan chain reordering algorithm; yield loss; Algorithm design and analysis; Circuit faults; Controllability; Fault diagnosis; Logic gates; Partitioning algorithms; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2013 18th IEEE European
Conference_Location :
Avignon
Print_ISBN :
978-1-4673-6376-1
Type :
conf
DOI :
10.1109/ETS.2013.6569355
Filename :
6569355
Link To Document :
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