Title :
Test generation for circuits with embedded memories using SMT
Author :
Prabhu, Shashank ; Hsiao, Michael S. ; Lingappan, Loganathan ; Gangaram, Vijay
Author_Institution :
Virginia Tech, Blacksburg, VA, USA
Abstract :
One of the important challenges in testing modern SOCs is the presence of small embedded memories. These memories are too small to employ memory BIST. Also, making these embedded memories scan-able or employing MBIST would increase the area overhead and/or test application time.
Keywords :
built-in self test; integrated circuit testing; integrated memory circuits; surface mount technology; system-on-chip; MBIST; SMT; SOC testing; embedded memories; memory BIST; test application time; test generation; Benchmark testing; Circuit faults; Electronic mail; Europe; Integrated circuit modeling; Logic gates; Vectors;
Conference_Titel :
Test Symposium (ETS), 2013 18th IEEE European
Conference_Location :
Avignon
Print_ISBN :
978-1-4673-6376-1
DOI :
10.1109/ETS.2013.6569390
