A DC-9.5GHz noise-canceling distributed LNA in 65nm CMOS

Author

Jianxun Zhu ; Krishnaswamy, Harish ; Kinget, Peter R.

Author_Institution

Columbia Univ., New York, NY, USA

fYear

2013

fDate

2-4 June 2013

Firstpage

177

Lastpage

180

Abstract

Summary form only given. A low noise amplifier is presented that uniquely achieves wide-band input matching and good low-frequency noise performance at the same time. Its topology is a hybrid of distributed amplifier and a common-source common-gate noise-canceling amplifier. The proof-of-principle prototype in 65nm CMOS operates from DC up to 9.5GHz with more than 12dB gain, achieves a minimum noise figure of 2.8dB, P_1dB of -7dBm, IIP₃ of +4dBm, consumes 18mW from a 1.4V power supply and occupies a total active area of 0.4mm².

Keywords

CMOS analogue integrated circuits; distributed amplifiers; field effect MMIC; integrated circuit noise; low noise amplifiers; network topology; CMOS; common-source common-gate noise-canceling amplifier; distributed amplifiers; frequency 9.5 GHz to 0 GHz; low noise amplifier; low-frequency noise performance; noise figure 2.8 dB; noise-canceling distributed LNA; power 18 mW; power supply; proof-of-principle prototype; size 65 nm; topology; voltage 1.4 V; wide-band input matching; Bandwidth; CMOS integrated circuits; Frequency measurement; Gain; Impedance matching; Noise; Topology; CMOS integrated circuits; Distributed amplifier (DA); Low noise; Low-noise amplifiers (LNAs); Low-power; Noise cancellation; Noise-canceling LNA; RF; Wideband LNA; Wideband matching;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2013 IEEE

Conference_Location

Seattle, WA

ISSN

1529-2517

Print_ISBN

978-1-4673-6059-3

Type

conf

DOI

10.1109/RFIC.2013.6569554

Filename

6569554