• DocumentCode
    625672
  • Title

    Adaptive Cache Bypassing for Inclusive Last Level Caches

  • Author

    Gupta, Swastik ; Hongliang Gao ; Huiyang Zhou

  • Author_Institution
    Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
  • fYear
    2013
  • fDate
    20-24 May 2013
  • Firstpage
    1243
  • Lastpage
    1253
  • Abstract
    Cache hierarchy designs, including bypassing, replacement, and the inclusion property, have significant performance impact. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the last level cache (LLC) performance. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing inherently breaks the inclusion property. This paper presents a solution to enabling cache bypassing for inclusive caches. We introduce a bypass buffer to an LLC. Bypassed cache lines skip the LLC while their tags are stored in this bypass buffer. When a tag is evicted from the bypass buffer, it invalidates the corresponding cache lines in upper level caches to ensure the inclusion property. Our key insight is that the lifetime of a bypassed line, assuming a well-designed bypassing algorithm, should be short in upper level caches and is most likely dead when its tag is evicted from the bypass buffer. Therefore, a small bypass buffer is sufficient to maintain the inclusion property and to reap most performance benefits of bypassing. Furthermore, the bypass buffer facilitates bypassing algorithms by providing the usage information of bypassed lines. We show that a top performing cache bypassing algorithm, which is originally designed for non-inclusive caches, performs comparably for inclusive caches equipped with our bypass buffer. The usage information collected from the bypass buffer also significantly reduces the cost of hardware implementation compared to the original design.
  • Keywords
    cache storage; cost reduction; memory architecture; performance evaluation; LLC performance enhancement; adaptive cache bypassing; bypass buffer; cache bypassing algorithm; cache hierarchy design; cache lines; cache replacement; hardware implementation cost reduction; high performance caches; inclusive last level caches; last level cache performance enhancement; upper level caches; usage information; Algorithm design and analysis; Art; Benchmark testing; Buffer storage; Coherence; Hardware; Resource management; Last level cache; cache bypassing; cache replacement policy; inclusion property;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on
  • Conference_Location
    Boston, MA
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-4673-6066-1
  • Type

    conf

  • DOI
    10.1109/IPDPS.2013.16
  • Filename
    6569900