First-Order Digital Phase Lock Loop with Continuous Locking

A zero-crossing digital phase locked loop (ZCDPLL) system with dual gain selection technique for fast acquisition, reliable locking and improved phase noise and jitter performance is proposed. The system is designed and simulated based on adaptive loop gain techniques. It utilizes the wide locking range properties and fast acquisition of the high gain loop and enhanced noise performance of the low gain loop. The simulation results confirmed the new system´s ability to switch between high and low gain loops in order to acquire fast acquisition, while keeping the loop in lock. In this approach the system will maintain the desired properties of fast acquisition and wide locking. These characteristics are normally in conflict with each other. The noise performance of the system has been tested and shown to give improved jitter and phase noise which makes the loop very attractive frequency synthesis and other communications and control applications.