MLC STT-RAM design considering probabilistic and asymmetric MTJ switching

Spin-transfer torque random access memory (STT-RAM) has widely believed as a promising candidate for the post-silicon nonvolatile memory technology. In many recent researches, STT-RAM has demonstrated many attractive characteristics, such as nanosecond access time, high integration density, adjustable non-volatility, and good CMOS process compatibility. As the distinction between the two boundary resistance states of the magnetic tunnel junction (MTJ) device continues to improve, multi-level cell (MLC) STT-RAM emerges as an interesting technology to pursue. However, since the resistance margin is partitioned into multiple segments for multi-level data representation, the performance and reliability of MLC STT-RAM cells become more sensitive to the MOS and MTJ device variations, as well as the thermal-induced randomness of MTJ switching. In this work, we report our recent study on the reliability of the read/write operations of the stacking MLC STT-RAM cells by consider the different variability sources. Our simulation result shows that although the stacking MCL STT-RAM has not yet satisfy the requirement of commercial product under the realistic fabrication conditions, it has shown the great potentials under careful design optimizations.