A merged first and second stage for low power pipelined ADC

This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique is also used for the reduction of power and noise. The proposed stage relaxes the requirement for the gain of opamp by about 6dB comparing to the conventional one. For verification, a 14bit, 200MS/s pipelined ADC is designed in a 130nm CMOS process. The simulation results show 73.4 dB SNDR with noise and 88.8dBc SFDR at 95 MHz input frequency. The pipelined core power consumption is about 42mW at 1.2V supply, and the whole pipelined ADC has an energy efficiency of 178 fJ/conversion-step.