Title :
10b 150MS/s 0.4mm2 45nm CMOS ADC based on process-insensitive amplifiers
Author :
Tai-Ji An ; Jun-Sang Park ; Yong-Min Kim ; Suk-Hee Cho ; Gil-Cho Ahn ; Seung-Hoon Lee
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
Abstract :
A 10b 150MS/s 0.4mm2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gain-boosting, pseudo-differential output pair, and continuous-time common-mode feedback circuits to overcome various performance limitations that are observed in deep nanometer CMOS technologies. The MDAC2 and MDAC3 share a single high-gain amplifier to reduce the input memory effect, chip area, and power dissipation. The measured DNL and INL are within 1.06 and 1.29LSB, respectively. At 150MS/s, the prototype ADC shows a maximum SNDR of 51.8dB and a maximum SFDR of 63.7dB with a 1.2Vpp sinusoidal input and consumes 47.3mW.
Keywords :
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; capacitors; circuit feedback; sample and hold circuits; CMOS ADC; DNL; INL; MDAC; SFDR; charge-redistributed capacitors; chip area; continuous-time common-mode feedback circuits; differential input signals; input SHA; input memory effect; nanometer CMOS technologies; pipeline ADC; power 47.3 mW; power dissipation; process-insensitive high-gain amplifiers; pseudo-differential output pair; size 45 nm; voltage 0.8 V; voltage 1.1 V; voltage 1.2 V; Bandwidth; CMOS integrated circuits; CMOS technology; Capacitors; Frequency measurement; Power demand; Prototypes;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6571855
