Title :
A 1.83 μW, 0.78 μVrms input referred noise neural recording front end
Author :
Jiangchao Wu ; Law, Man-Kay ; Mak, Pui-In ; Martins, Rui P.
Author_Institution :
State Key Lab. of Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China
Abstract :
This paper describes a neural recording front end for both Local Field Potential (LFP) and Spike Potential (SP) recordings, which range from 0.1 Hz ~ 200 Hz and 200 Hz ~ 10 kHz, respectively. Based on the capacitively-coupled chopper instrumentation amplifier (CCIA) topology, a ripple reduction loop (RRL) is used to suppress the chopping ripple. A DC servo loop (DSL) that utilizes pseudo-feedback to achieve a very small unity gain bandwidth with reduced capacitor size while consuming only 12 nA is proposed. The proposed CCIA is implemented in a standard 0.18 μm CMOS process. Simulation results show that with a total power consumption of 1.525 μA from a 1.2 V supply, a NEF of 2.73 (LFP) and 2.6 (SP) can be achieved.
Keywords :
CMOS integrated circuits; capacitors; choppers (circuits); coupled circuits; feedback amplifiers; instrumentation amplifiers; prosthetic power supplies; recording; CCIA; DC servo loop; DSL; LFP; RRL; SP; capacitively-coupled chopper instrumentation amplifier topology; capacitor size reduction; chopping ripple suppression; current 1.525 muA; current 12 nA; frequency 0.1 Hz to 200 Hz; frequency 200 Hz to 10 kHz; input referred noise neural recording front end; local field potential; power 1.8 muW; pseudofeedback utilization; ripple reduction loop; size 0.18 mum; spike potential; standard CMOS process; voltage 0.78 muV; voltage 1.2 V; Bandwidth; Capacitors; Choppers (circuits); DSL; Gain; Instruments; Noise;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6571866
