A high throughput ASIC design for IPv6 routing lookup system

Author

Yi-Mao Hsiao ; Yuan-Sun Chu ; Chao-Yang Chang ; Chung-Hsun Huang ; Hsi-hsun Yeh

Author_Institution

Design Autom. Technol. Div., Inf. & Commun. Res. Lab. (ICL), Hsinchu, Taiwan

fYear

2013

fDate

19-23 May 2013

Firstpage

505

Lastpage

508

Abstract

This paper presents a cache-centric, hash-based architecture within a application specific integrated circuit (ASIC) implementation for IPv6 routing lookup system. In ASIC, the binary content addressable memory (BCAM) as cache memory has a hit ratio of up to 80% with a FIFO replacement algorithm. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The results of postlayout simulations show that the ASIC operates in 3.6ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100 Gbps networks. The routing table only needs 10.24KB on-chip BCAM, 20.04KB offchip TCAM and 29.29MB DRAM for 3.6M routing entries in the proposed system.

Keywords

DRAM chips; application specific integrated circuits; network routing; table lookup; DRAM; FIFO replacement algorithm; IPv6; binary content addressable memory; cache-centric; high throughput ASIC design; offchip TCAM; on-chip BCAM; routing lookup system; ternary content addressable memory; Application specific integrated circuits; Cache memory; Computer architecture; Generators; IP networks; Random access memory; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6571891

Filename

6571891