Memory-efficient scalable video encoder architecture for multi-source digital home environment

In this paper, a memory-efficient and low-complexity architecture is proposed for the scalable video encoder, achieving the requirement of the multi-source digital home environment. The proposed very-large-scale integration architecture of the scalable video encoder is implemented in TSMC 0.18-μm 1P6M CMOS technology. The proposed hardware is synthesized under 0.18-μm CMOS technology; resulting throughput is 93.3M samples/sec, occupying 182K gates. Resulting power dissipation is 42.13 mW, operating at 150 MHz clock source. The performance of proposed work (the throughput) meets 1080p@30 fps real-time encoding, constrained by wireless high definition video interface for mobile environment.