DocumentCode :
626617
Title :
A 34.1fps scale-space processor with two-dimensional cache for real-time object recognition
Author :
Youchang Kim ; Junyoung Park ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
689
Lastpage :
692
Abstract :
A scale-space processor with two-dimensional cache is proposed to achieve real-time object recognition in HD 720p images. Scale-space is the most commonly used concept to achieve scale-invariant property in object recognition, however its high computational cost makes it hard to implement a realtime object recognition processor. We employ hierarchical convolution unit (HCU) which computes multiple pixels in a single cycle with various kernel sizes. In addition, two-dimensional cache (T-Cache) supports accessing vertically consecutive data from any image window size with reduced area. A pre-fetch controller for the proposed cache improves the hit rate by exploiting the sequential access pattern of convolution tasks. As a result, the scale-space processor implemented in a 0.13μm CMOS technology achieves 34.1fps on a HD 720p image while consuming peak power of 84.5mW.
Keywords :
cache storage; object recognition; HD 720p images; hierarchical convolution unit; kernel sizes; power 84.5 mW; real-time object recognition; scale-invariant property; scale-space processor; two-dimensional cache; Adders; Computer architecture; Convolution; High definition video; Kernel; Object recognition; Real-time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6571940
Filename :
6571940
Link To Document :
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