Design of reliable 2×VDD and 3×VDD series-parallel charge pumps in nanoscale CMOS

With aggressive CMOS transistor scaling, reducing the risk of transistor breakdown has been becoming paramount in nano-era VLSI circuit designs. The paper presents design techniques and considerations on achieving reliable high-voltage series-parallel charge pumps. It adopts a stacked-MOSFET structure to achieve reliable 2×V_DD and 3×V_DD high-voltage switching. In addition, capacitor voltages are efficiently utilized to drive the power switches effectively and safely, such that any node-pair voltage of MOSFET power switch can be kept within the rated supply voltage (V_DD), defined by the fabrication process. Furthermore, over-voltage stress and hot-carrier degradation can be overcome even in the transition phases. To verify the design concepts, a 3×V_DD charge pump is designed with IBM 130-nm CMOS process. Simulation results demonstrate that the proposed charge pump provides a maximum output voltage of 4.5V and delivers up to 200μA load current with an input supply of 1.6V and a maximum efficiency of 81%.