A low-power, ultra low-offset, 16.5-bit, ΣΔ ADC for coulomb counting and fuel gauge applications

A converter macro is presented. It has been used as part of a current-to-digital converter and as part of the voltage measurement unit for battery charge control. It uses a split decimation filter, which improves the resulting SNR when system level chopping is performed. Fabricated in a 130nm CMOS process it consumes only 30μA/24μA (with or w/o reference buffer) from a 1.35V source. Specially tailored to be connected to low impedance sources, it accepts small input signals with a linear range (-3dB_FS) in the order of 100mV_peak. It has an SNDR > 97dB @ -3dB_FS in a 1Hz BW, a low-frequency CMRR > 100dB due to double sampling, and a low-frequency PSR > 80dB_FS for a 20mV_peak supply disturbance (operating at maximum input level). The chopping results in an average offset in the order of 200nV.