A power-efficient scan tree design by exploring the Q´-D connection

Full scan design is usually time-consuming. Scan tree-based architectures can be applied to reduce test time, but few of them are power-efficient. Many low-power techniques have been proposed for scan chain design, while they are not applicable to scan tree architecture. To achieve a time-efficient and low-power scan design, in this paper, we propose a scheme to reduce the test power consumption of scan tree design by exploiting the Q´ ports of scan flip-flops. As the structure of scan tree is not affected, the scheme resembles the time-efficiency of scan tree design. The modification for low power maintains the order of scan cells. It thus avoids the consequent design overhead due to scan reordering. Furthermore, no extra hardware is introduced. Experimental results on ISCAS´89 benchmarks show that 8.38% weighted transitions during test application can be reduced on average.